System Verilog Assertions.
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
Design FSM for some problems
they asked about UVM architecture and classes concept .
Systemverilog, UVM, prime number generation, FSMs
Write a decimal to hex function in C
Logic question to verify the design How would you verify 3 blocks with incorrect label ? suppose one with apple 2 with orange 3 with apple & orange.
ahb protocol.about the work exp.coverage.constraints.assertions.polymorphism
There's a circuit diagram of two parallel capacitors with different charge voltages, connected by a transistor. What happens to those two voltages when the transistor turns on?
Why do you feel like this role is suitable for me?
First Question: Python question: Find all unique elements listLang = [CPP, PYTHON, JAVA, JAVA, CPP] Second Question: Public int foo(List<Integer> nums){ Int x = -1; Int y = -1; For(Integer num : nums){ If(x < num){ Y = x; X = num; } Return y; { What is the code supposed to do? What is the problem? How can you fix it? (They said they weren't supposed to ask this question, they were curious.
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