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Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
Find a bug in Fifo verilog code
What Is UVM? What Is the Advantage Of UVM?
Are you bilingual? Spanish or Vietnamese
A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
Given 3 blocks, asked to make signal connections among them and what is my approach to verify
they ask me my preference of work
What I know about verilog
Name last job experience and some other questions
develop exor gate using 2:1 mux and draw the circuit
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