Classes, fork_join, randomization, functional coverage , OOPS
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
1. Write a code to generate a o/p. every time input is 1'b1 output will get asserted next cycle & output will toggle to 0 only when input toggles. 2. Cache schemes. 3. Concept about Virtual, data structures used in scoreboards.
Code some black box RTL in verilog
Not any in particular
What is the difference between combinational and sequential logic?
1. finding the probability of possible combiations of a radom variable with given constraints. 2. Question related to System Verilog Assertions.
I think nothing... but few USB and DDR related stuff... as it was part of my resume...
All the problems are quite common . But some C program questions , such ass what is interrupt
Design a circuit to generate a pulse whenever the input flips.
There were not any difficult questions, just difficult interviewers.
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