digital ,verilog ,sv, c, computer architecture
Verification Engineer Interview Questions
3,713 verification engineer interview questions shared by candidates
Interview was completely based on MPLS and IGP
Tomasulo algorithm and resume project/ experience
Where do you see yourself in five years
they ask basics and practical questions. also check coding and logical questioning.
I Am Trained Asic Verification Engineer.. They Ask Some Digital Electronics Questions.. They Will Judge You On Basis Of Your Digital Electronics Knowledge .. Even They Didn't Ask Me A Single Question From Verilog, System Verilog And UVM ... Which I Know Batter .. I AM Not Good In Digital Electronics
what are the array meand
Explain your approach when you encounter an unusual anomaly? How do you resolve the problem?
Design a Neural Network for a system.
1. Memory design and block diagram 2.Verilog programming 3.C++ (oops concepts) 4.SV & UVM components
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