Common elements in 3 arrays.Sum of the array.
Verification Interview Questions
3,713 verification interview questions shared by candidates
What is regression testing?
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
How to bulid a round robin
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
1. Describe verification process of some modules 2. Describe typical test environment (monitor, driver etc) 3. Some common SystemVerilog problems and questions
What is the difference between Mealy and Moore machines?
Uvm phasing process, different phases in uvm
why should we hire you
where do you see yourself in 5 years
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