UVM based questions and Assertions and constraints
Verification Interview Questions
3,713 verification interview questions shared by candidates
Write a SV model for comparator
Create a 4-to-2 priority encoder using only basic logic gates. Then use those encoders and MUXs to create a 16-to-4 encoder. Create a state machine to show if a binary number is divisible by five.
Assertion to check the waveform
What is the difference of function and task in verilog
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Q. Describe your test plan for a FIFO
Why do u wanna work with us??
There were questions about: -how I'd dealt with difficult situations in past positions, experiences with managing others -how I would manage setting aside "work flow" time in a busy, open office environment -how I would go about selecting individuals for my team
Sv and UVM project knowledge protocol mentioned in CV
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