Basically they wanted to see if I can understand a large code base quickly
Verification Interview Questions
3,713 verification interview questions shared by candidates
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
The questions were more into the current project and tool used.
Sv and UVM concepts
More on digital if you are a fresher SV , UVM would provide better opportunity
1. Self Introduction 2. Difference between Synchronous & Asynchronous Assignment 3. what is cache memory 4. How many caches do we need in the CPU 5. what is Threading in H/W RTL Design 6. what is a pointer and with that can we print data & its address 7. pattern detector - 10011 use any FSM (Mealy/Moore) and its Verilog code 8. 4:2 priority encoder using 2:1 mux
Questions on FSM, STA, FPGA, Verilog Basics, SV Basics,
Virtual interface, Functional coverage, TB
Amba protocols related Constraint for even and odd with modulo operator
Blocking vs nonblocking Flip-flops vs latch Uvmphases
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