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Verification Manager Interview Questions
3,719 verification manager interview questions shared by candidates
Tell me about a time when you created a product for a company that made your job easier; what was it and how did it work?
what did u understand about this Role?
UVM Phases, why do we use Virtual, Constraints , Use of randc , assertions , how do you override , how do you analyze verification metrics, callbacks
Blocking vs non blocking in Verilog and Logic Design. Pipelining concept. Basic algorithms, time/space complexity. Virtual functions in C++
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
What is an isolation cell?
Setup/hold time problem; meta-stability; 5-stage pipeline
data types in system verilog, test cases for memory designs, flipflop design
How do you find common elements between the arrays? reduce the complexity, asked me to write the code
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