Edge trigger variation coding in RTL
Verification Manager Interview Questions
3,719 verification manager interview questions shared by candidates
Write a test plan for asynchronous reset flip flop
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
how to resolve the issue with a malfunctioning vending machine with a pending deadline
- More details about projects and experiences on the resume - 3 questions DSA related to embedded systems (only walking through ideas)
Questions on writing constraints for the given sequence.
System Verilog Assertions- FIFO Based
We want to send a specific amount of data and to prevent errors, we want to divide the data into several segments randomly within a certain size range. How can we perform this division so that there will definitely be enough data for all the remaining packets?
first was an assembly question, to implement multiplication with certain commands and few registers avaliable. second question was to build a xor gate with 4 wierd components which are sometimes Z and sometimes have output.
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