1. Difference between inter assignment and intra assignment delay 2. Blocking and Non- blocking procedural block 3. How to design AND gate using MUX 4. Signals used in FIFO. 5. Do FIFO required address or not? 6. What do you understand by synchronous and asynchronous circuit. 7. How can we disable the randomisation ? 8. Why we use virtual interface in verification environment? 9. How to select and give in the particular testcase which were generated in generator block?
Describe a color to a blind person.
define tlm fifo's?
Digital and SV ,UVM verilog basis
1. Overall was on project 2. UVM methodologies and SV 3. Have been asked on logical reasoning 4. Queries on verilog, RTL coding were asked. 5. OOPS based concepts ,Polymorphism, Inheritance, Arrays methods, stacks ,Queues, Multidimensional arrays ,Vectors
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
Where do you see yourself in 5 years?
How to have accurate testing when you a large test case to cover.
Lcm, Swap, Factorial for C coding Write constraints in system verilog
System verilog,uvm,verilog constraints and assertions , about projects
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