The other 3 questions had design scenarios where I had to plan testcases to check their correctness...
Verification Manager Interview Questions
3,716 verification manager interview questions shared by candidates
Questions related to a verilog project I did in college.
How many times does the clock hands cross each other throughout the day?
Create an FSM for detecting a sequence
My previous experience, as well as a few mock examples related to verification and what my process would be
Asked questions on Risc-V pipeline, coding, verilog, etc.
each interview had at least 3 RTL design questions
Give a detailed example of a test you wrote
Implement a state machine that detects modulo 5
You have a module that gets 4 input bits and returns the number of lower bits that are logic ‘1’, along with a valid bit. Expand it to 16 bits.
Viewing 2961 - 2970 interview questions