verify a FIFO using formal verification techniques and methods to resolve complexity
Verification Manager Interview Questions
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Implement using simple digital components a system that only transmits a stable signal (only if the logical value is stored N times)
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
write code which returns error if we got 10 packets within 10 seconds
Uvm phasing process, different phases in uvm
1. Describe verification process of some modules 2. Describe typical test environment (monitor, driver etc) 3. Some common SystemVerilog problems and questions
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
How do you handle conflict in the workplace?
Print the relevant parts of this data file out in X,X,X format from a given list that has extra/missing bits of information.
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