mentioned above in detail .. ..
Verification Manager Interview Questions
3,713 verification manager interview questions shared by candidates
1. basics of Verilog. 2. verification coding questions. 3. coding question in Verilog.
What assertions did I write to verify functionality of my SV projects? Sequence detector 10110? What is FSM-D?
What is carrier aggregation,MIMO, OFDM , RACH procedure. What is the difference between enum and a macro difference between struct and union difference between interface and abstract class and be through with every line on your resume.
Fully explain what kind of projects have you done.
Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
Output the sum of the largest series of consecutive values, in an infinite arbitrary series of numbers.
Create an application like Visio.
swap a string such that it will appear in reverse
Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
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