Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Verification Manager Interview Questions
3,712 verification manager interview questions shared by candidates
Draw the IDD diagram (current as a function of time) of an inverter when the input switches from OFF to ON.
Does Latch have a concept of setup and hold time. If yes explain. If no Explain.
related to projects and your role in the project
Difference between AXI and AHB and based on AXi channels
Shuffle a array Given an array, write a program to generate a random permutation of array elements. This question is also asked as “shuffle a deck of cards” or “randomize a given array”. Here shuffle means that every permutation of array element should equally likely.
Basic C Verilog Computer Architecture
They asked me about my internship experience.
Discussed C++ Pointers. I was not expecting that topic. Also, Async Fifos, Dynamic Arrays in SV.
digital circuits and verilog , c language
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