set up time and hold time
Vlsi Design Engineer Interview Questions
303 vlsi design engineer interview questions shared by candidates
Basics of C language, Detailed explaination of projects
Basic vlsi questions , project questions
How do you replace cat with dog in perl?
What happens if you don't give a default statement? How is latch inferring bad for the design?
All The Digital Electronics topics
they asked about the asic flow, physical design steps, went a bit deep into those. then asked about STA and questions related to the projects done.
design logic gates few questions on Verilog coding
there were many questions on basic verilog and vlsi which i dont knew.
whats rtl level designing in verilog
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