asked digital electronics, rtl design, coding, tricky questions
Vlsi Design Engineer Interview Questions
303 vlsi design engineer interview questions shared by candidates
How PLL is implemented in VHDL?
Digital electronics, verilog,static timing analysis
difference between single precision and double precision?
beta of a bipolar transistor depends on... there were options
Tell me your name please
Interview 1 1.What is cmos 2.Why we have pmos pun and nmos as pdn 3.How pmos is good at giving logic 1 and nmos good at giving logic 0 4.Explain set up and hold time and prograpagation delay with waveform 5.What is PLL, what are the components of PLL 6.What is frequency divider. 7.how do u reduce power consumption in cmos . 8. Multi threshold cmos 9. Asic design flow 10. Difference in verilog tb , sv tb 11. Why we go for uvm 12. About project, who will u extend ur project u have any idea. INTERVIEW -2 1. difference between program block and module 2. Write a code and explain event schedulers in verilog and sv 3.what race condition in verilog 4. How u overcome race condition in sv tb 5. How uvm is efficient than sv 6. Current mirror and draw a current mirror circuit 7. Opamp . Applications 8. Enhancement mode mosfet depletion mode mosfet 9. Flow of uvm tb 10. Flow of sv tb 11. How u will avoid race condition by applying inputs in verilog tb 12. Difference between fet and bjt 13. Project on apb ahb,Soc , Pipeline processor . How normal cpu works 14. Difference between tunnel fet and finfet 15. Encoder and decoder. Real time application
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digital electronics, digital vlsi design, analog vlsi design, physical design fundamentals, static timing analysis, aptitude and CMOS fundamentals focused mostly on resume and VLSI technical questions. Questions on CMOS inverter, Antenna effects, PNR flow, Shell scripts, STA fundamentals. Aptitude problems, Problems on decision making with given situations and circumstances.
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