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Vlsi Design Engineer Interview Questions
303 vlsi design engineer interview questions shared by candidates
Technical question
D flip flop, Setup time, Hold time, Finite state machine, Pattern Generator verilog code
Power Aware Cells, Verification, SOC JTAG, connectivity. Test Data Volume, EDT bypass, TDF<SFA. Penalty Flops etc.
Explain Kirk effect ??
request to tell about things i did
Q: Explain the concept of setup and hold time in detail.
2 ways of constructing Not from NAND?
In a series circuits with <voltage source> <capacitor 1> <capacitor 2>, what is the voltage across capacitor two. The point of this was to show that the voltage depends upon the value of the other capacitor, and this relates to what happens in a NAND gate as the signal switches from positive to negative.
VLSI Based
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