digital electronics, digital vlsi design, analog vlsi design, physical design fundamentals, static timing analysis, aptitude and CMOS fundamentals focused mostly on resume and VLSI technical questions. Questions on CMOS inverter, Antenna effects, PNR flow, Shell scripts, STA fundamentals. Aptitude problems, Problems on decision making with given situations and circumstances.
1. Tell us about yourself 2. What are your projects? 3. what is Cmos? 4. about Flipflops and latches
Design aschronous d flip flop
what do you like to do
What is JTAG What is cluster based design? Describe about cluster based region? 2. What are the problems are faced when placing long net of FF to FF path and Short net of FF to FF path? 3. Is timing driven placement advantageous over the functionality based placement? Explain briefly. 4. Explain In Place Optimization and Timing Delay? 5. How to do Congestion optimization and balance slew?
what are the basic logic gates and why nand and nor are tht universal gates
Tell me about your graduation project at the university?
What are the System tasks in SV
what is the extreme negative value of the two's complement number xx.xxxxx?
Digital electronics basics and verilog basics
Viewing 261 - 270 interview questions