I was interviewed for a verification role at Sheffield. It was a virtual interview. There were two rounds. The first round with the hiring manager (initial screening). The questions were mostly from my CV to check if I have really worked on some stuffs. After a few days the HR organized a second round of interview. The interview was pretty straightforward with two engineers. I managed to answer most of their questions but not sure of the reason for rejection. Maybe they were looking for a more experienced candidate.

this is campus interview , starting asking me the reklevant coursework i have in my curriculum and breif intro about them ,like low power vlsi design -what they have taught us and asked about how dynamic,static ,short circuit power dissipation happens in an inverter . ,how to reduce them , power reduction techniques at logic level ,architecture level ,after this gone for verilog , basic bolcking and non blocking ,traffic signal using delay ,projects on digital design using verilog or system verilog