Broadcom interview questions

The interview process was an online application for a position as RTL verification advertised by my University placement centre. I have been invited to an assessment day with two other people. The day was mostly composed of individual technical panel interviews in which I was asked to solve small RTL design problems with the aid of pseudocode or other code/mean. I passed the assessment day, but they realised I was more keen on another position in the company and they put my application on hold. After 2 weeks I have received another job advert for RTL design instead, which I apply to. I was invited to a panel interview with senior members of the team. Mot of the interview was focused around a set of paper with different RTL design problems for me to solve. Afterward I was asked normal questions such as why I was applying for Broadcom., and the usual one-two competency questions.

Asked about projects on my resume. And then technical questions: 1,mismatching in layout: Prov is one contributor. (glitch?) 2,how to decrease power, dynamic and static (sub threshold), Why can use CMOS 3,logic design: change DFF in counter into TFF, then there are only three states. 00->01->11 4,how to minimize noise using CMOS 5,setup time and hold time, what does skew influence setup time and hold time 6,What factors influence system frequency. I answered setup time. 7,asked my project, size of whole layout os SRAM and final project in 477. 8,how to decrease delay, I answered using larger size. update: increase I, such as size, Vdd, logical effort, decrease load. pipeline , parallel