what are your strength and weakness ?
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
Questions were related to FPGA constraints and Verilog coding procedures as well as LUT's.
ask to explain in detail about the exixting knowledge
What is the use of priority encoder
CDC, FIFO, FSM, STA concept.
UVM, Functional Verifications, Personal skills questions and pass experiences.
the flow of ASIC and from synthesis to GDSII
System verilog and c based questions Fork join , assertions , coverage
Static timing analysis, setup time, hold time, verilog questions, puzzles, clock domain crossing, synchronisation
The standard, how to design an async FIFO?
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