Create an inverter with a 2-input NAND gate
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
fork-join use in a sequence. UVM Test bench architecture. Virtual interface requirement. etc.
Can you describe a challenging ASIC design problem you faced and how you resolved it?
5-year goal and about personality. they also asked about what challenged I faced in my day to day work and within a team.
No difficult questions
Techniques to reduce power dissipation
implement a counter, analyze signal diagram
AND & OR gate from 2-1 MUX.
1. what is the max freq of a given circuit.(setup and hold analysis related) 2. one question was related to stuck at fault. we need to find out the input test pattern in order to detect the stuck at fault of given circuit. 3. IN1?A:IN2?B:IN3?C:1'b0 How many 2:1 mux are required to implement this? 4 one question was related to FIFO Depth calculation. 5. In a given circuit to meet timing how many no of re timing flops need to be inserted?(you should be clear with setup analysis) 6. Questions were related to transistor sizing and cache memory hit and miss ratio. 7. One puzzle was also asked of Annual function and van related(don't remember exactly. :p)
Describe an application where you would use a latch?
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