Q: How do you construct a 4x1 MUX using 2x1 MUXs
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
I report only the technical questions: - how the asynchronous reset can cause issues in a synchornus system - Pipelining (open question) -definition of setup time and hold time -Techniques to reduce power consumption (open question)
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
The second was about state machine, how to output true for every two consecutive 1s.
use 4 bit multiplier to build 8 bit multiplier
Setup and hold time - definitions; there is a branch with one path being setup critical, and another with a hold violation. Given a buffer, where will you place it if both paths should not have violations?
Trick question on FIFOs.
The interview was more related to what you wrote in written exam.
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