Difference Between Associative array and Dynamic Arrya
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Based on algorithm implementation at hardware level.
Swap via value versus reference coding question. Design question about feeding data from producer to consumer (answer uses buffer)
What are you currently working on?
They asked me Static timing analysis question.
Have you built a library before
Ffs - implement it in rtl including 8 elements including how to test your answer . Find first set . First implement with gates than with system verilog there is many ways to solve this q
Computer architecture, cache coherence, CPU design, pipelining
Leetcode questions and verilog module coding.
They asked for the logic to get the maximum element in a shifted sorted array.
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