Mix of technical and behavorial. Verilog basics, RTL, STA, etc.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Comp arch, C++, OOPS, Verilog, STL
Formal Verification, Assertions based questions based on the resume and projects
describe what is virtual function. and difference between that and pure virtual function?
difficult
Define setup and hold time.
Is LPDDR5 PHY backward compatible?
Questions on Low power design.
explain and draw circuits/diagrams from projects on resume
cmos fundamentals, rtl design, verilog, physical design flow, static timing analysis and some aptitude questions
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