Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Calculate the number of tag bits in a cache address given its size, associativity, and block size.
Write a function that takes an integer as input and returns the closest multiple of 16 (any language).
Implement a circular FIFO buffer using DS of your choice
Explain metastability and crossing between clock domains
Design basic state machines (mealy moore) and give the circuit implementation
what's the logic of a mux
Design a state machine to implement back face culling of polygons in a simple graphics renderer.
Floating point representation and issues.
If you had a risc instruction set architecture with a 4 bit ASLU unit, how would you extend your architecture to include an 8 or 16 bit ALSU unit without heavily modifying the hardware?
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