Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Antenna Effect, latch up
Explain about the AXI write process with signal descriptions
Do you understand timing constraints. Asked a few questions about them.
Basic FIFO and CDC questions
Gave a standard fifo design and told me to explain how i'll write testbench for that
design uvm driver
Explain POCV coefficient based calculation for an actual timing report.
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
Very theoretical questions about FF level design.
Viewing 791 - 800 interview questions