pipeline, fifo in registers/ram, hold/setup and how to correct violations, my undergraduate projects, Circuit with different clock frequencies, circuit with single frequency but clock skew and more.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Introduce your education background
electronics the technical questions like find the output of flip-flops find the output at a specific clock cycle combinations of flip flops and mux simplifications of gates transmission gate problem basic electronics like temperature were given flipflops and interview time played a dominant role in the first round
VLSI, Device Physics, Cadence, Verilog and C Programming.
State machine, gate level design
Explain Setup and hold for a latch.
Raised Cosine Filter; roll--off factor; 100 doors puzzle
transistor sizing for a NAND gate
Design a FIFO hardware
False paths and Multiple cycle path examples.
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