Why you do clk gating in your design
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
How to determine which register you want to gate in netlist ?
What gates would you use to make a full adder
Static Timing Analysis, Setup time, Hold time, Clock gating, Clock Path Pessimism Removal, Digital design flow, Vmin
How often do you use the digital programming software?
Setup and hold violation of given circuit
How to verify a fifo?
Create a module that implements a vending machine.
Do you have any experience with verification?
Tell me about a time when you faced a challenge.
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