Design a Counter verification environment.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
I was asked to write the RTL code for an asynchronous receiver in Verilog
From basics to complex fundamentals
Q. Design a 16X1 MUX using 2X1 mux, How many of need? Q. Many More.
What are your weekness and how can you surpass them in work environment?
Had to fill in a truth table of a multiplexer
What it a flip flop and what does it do
design a trafffic light controller
Qhat is your strength? An example of the time that you take initiative? What is your weakness?
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