Computer Architecture, Verilog
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
setup and hold time -implementing and gate using mux
setup time hold time, implement and gate using mux 2-1 and asynchronous fifo implementation and MIPS data path
Asked about clock domain crossing, asynchronous clocks, and difference between sequential and combinational logic.
How do you access a register and confirm it is 12 bit or not?
verilog code for mux,FSM,encoder,clock generator
Mostly about verilog, Problem solving skills
Ask about all vlsi field and digital logic design
How would you build a 4 to 1 mux with only 2 to 1 mux modules?
How would you build a sequential block and combinational block in verilog? what will you use "always@ * "?
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