Uvm based events, clk generation, how would you verify a given circuit
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Asked me about my courses at my university. Did you take any verification course. Which university you did in your bachelors in. Why do you like verification?
Questions on digital electronics ,aptitude ,logical reasoning etc
What was the most challenging design problem you ever had to solve?
Set up hold while the output of second ff is used as input of the first ff
Projects discussion. Interview questions are based on STA, CMOS , Low power, Verilog coding Clock domain crossing, Clock Tree synthesis & Crosstalk
2 questions- one about setup+Hold and another about implementing logic with 8 bit input that counts how many times the same numb have appeared - known that it is less than 10 times
Design a logic that detect three asynchronous pluses that can came at anytime with one counter. Set up hold, cdc questions Verilog questions Lint
Questions on constraints and assertions
Questions regarding library creating and area of the cells in the library
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