The first one was about implementing a NOT gate with MUX.
Asic Engineer Interview Questions
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Round 3 1- Add 7 bits using 4 Full Adders 2- two Pipelines runnign parallely. 128 Bit register file. 4 read ports n 2 write ports. Convert it into 4 reg files with one read n one write ports for all. Find adv and dis adv. 3- Design a divide by 3 FSM checker
for phone interviews, basic data structure algorithms. 1. Reverse singly linked list. Onsite was more difficult with a bit of algorithms, computer architecture, design verification, and OOP.
How do you as a back-end designer work with front-end (RTL/Synthesis) designers to solve tough timing problems, for example, under what circumstances do you absolutely need them to solve on their side? What information or files do you provide to them?
Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
Typical timing probs (fix hold time and setup time violations, power saving techniques, jitter, skew) Some simple comp arch (5 stage pipeline, hazards and how to fix them, VM) HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew and explain in detail.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asked about Cache implementation (since I had a project on cache implementation using verilog)
In C, write code to find out if a string is palindrome or not
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
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