2. CDC and Types of synchronizer
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Focus mostly SystemVerilog, methodologies and server processor architecture.
Problem solving approach Core VLSI concepts
Genral questions 1 setup time hold time 2 verilog basics verilog caculating (a+b)/2 or (a+b+c+d)/4, how to round 3 what 's the use of arbitrary 4 vending machine state machine 5 architecture pipeline
How can you reduce the delay of an inverter?
What is salicide layer? How is it related to self-aligned gates?
explain the project I did and DSP, FIR, FFT question
difference of function and task in Verilog
Setup and Hold time constraints
Counters, Flipflops, Latches, 32:8 Bit converter, State machine design, VHDL - Process statement, seuential logic, combo logic implementation, Functional coverage, code coverage - which coverage is crtitcal for verification sign-off and why ? , Different coding styles for FSMs, DV Environment diagram and explanation of last project in last company,.
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