How to determine cache size using a C program?
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Design a bitstream pattern detection finite state machine in the HDL of your choice.
Explain Tomasulo completely, SRAM design, cmos gate optimization, tools and constraints, semiconductor device characteristics, process corners etc were the topics covered
Name all the ROB entries in Tomasulo
Draw a diagram of an in order pipelined CPU and describe how instructions flow and execute.
1)why clock tree has inverters and not buffers? 2) structure of buffer internally 3) swap VDD & GND for inverter - describe the output 4) major elements to consider when building clock tree 5) why insertion delay is important? 6) CRPR 7) skew vs jitter RTL round 1) always block sensitivity list 2) latch inference 3) basic pipeline stages 4) hazards in pipeline 5) timing feedback to rtl PD round 1) basic Perl/python code to parse files and print data 2) regexp example 3) timing basics - aocv, pocv 4) how and why derating is done Manager interview - Resume related Timing round 1) timing driven restructuring example 2) identifying critical path in the given design 3) reordering of inputs based on criticality 4) how does transition affect cell delay 5) how can we vary transition to change setup and hold time Power round 1) multi VDD design basics 2) power gating 3) structure of level shifter 4) IR drop and EM problems 6) antenna violation 7) leakage power and it’s components RTL round 2 1) showed 2 timing paths and asked to identify the issues in the path 2) write an algorithm to store elements in a memory 3) reg array vs reg latch
Everything was fairly basic, if anyone's familiar with using a windows or a mac the questions are easy to answer
Verilog System Verilog Timing questions on VLSI Few logical question
Describe what IR drop is and factors that contribute to it.
Mesi Moore and mealy Coding
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