How many blocks are in an N way set associate cache?
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Describe in-order and out-of-order execution.
what need to be concerned when you design multiple execution
What is the probability that we going to have a hit on a cache if the TAG is XXX on a 32 or 64 bit ?
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
How to design an 64 bit adder if only given a 32 bit adder. After you design it, you will be asked how to verify it. The verification maybe related to SystemVerilog.
Different ways in which you can make an Single cycle processor increase throughput?
Pipelining, Cache, Virtual memory, Compilation steps, C keywords Verification Concepts- SystemVerilog, Assertions, UVM
What are the stages of pipelining
What is a cache ?
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