Basic Computer Architecture questions. How to extend a 5 stage pipeline to 6 stages. Effects of doing that etc. A few programming questions.
Cpu Verification Engineer Interview Questions
83 cpu verification engineer interview questions shared by candidates
Pipelining, latency and throughput, Cache, types of cache, problem on set way associative cache, interrupts, Virtual memory, page fault, project.
Q: Register renaming. How it works
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
What is a hardstuck bug you have encountered during a project?
Compare and contrast write-through and write-back caches.
Calculate the number of tag bits for an 8-way set associative cache with 32-bit virtual addresses that is 16kB.
How to write an assertion in SystemVerilog
Some verification related questions were asked?
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
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