First interview - I was asked to write pseudo code for memory allocation (like malloc/free). Second interview - I was asked to describe verification environment for a FIFO, considering sync/async. And to write a UVM monitor.
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
If you had to choose between two vacuums, same price, what would be some of the things you would consider?
what is a uvm agent?
Write a scoreboard in SV or UVM for simple alu where there is an 8 bit input that is changing value every clock cycle and the output should be equal to sum of previous 5 inputs.
Tell me a bit about yourself.
Immediate vs. Concurrent Assertions .
What is a pipeline driver?
I shared my experience in the projects that I worked on so far.
design question - design a system to identify if input bitstream is divisible by 5 - taking a 16bit stream, programming - print matrix spiral, etc. Also assertion questions, UVM
Describe fully how a processor works in as much detail as possible.
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