General questions in Python, C, Verilog, and SystemVerilog.
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
UVM Phases, why do we use Virtual, Constraints , Use of randc , assertions , how do you override , how do you analyze verification metrics, callbacks
How to use muxes to implement an XOR gate?
coding questions consists of - creating sequences - creating constraints for a given problem - creating an algo for data query
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
Describe fully how a processor works in as much detail as possible.
Leetcode easy questions were asked
- More details about projects and experiences on the resume - 3 questions DSA related to embedded systems (only walking through ideas)
what is a uvm agent?
what is your research area?
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