Tell me about yourself and then questions on verilog
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
Verification basics related to SV
write constraint for memory system
1. introduction and motivation 2. what's the verification life cycle and some behavioral questions 3. this's more like the data scientist introduce their process to me 4. write a python program that when it's intialized the anamal in the zoo could do it's action 5. behavioral questions
Resume - past experiences and projects
What challenges do you see in a cross-team effort for a verification project?
They gave me a design problem and kept on telling me to optimize it
UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
it was not that difficult.
Viewing 2311 - 2320 interview questions