Design Verification Engineer Interview Questions

3,719 design verification engineer interview questions shared by candidates

Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.
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FPGA Verification Engineer

Interviewed at Ciena

4.1
May 7, 2014

Mostly asked basic digital design questions. Draw a sequential circuit, what is the makeup of an FPGA (LE, Registers etc), Draw a mod 10 counter, draw the schematic for a half adder. Once i drew the schematic for it i was then ask to draw it as if i had only NAND gates.

I was asked to implement a 4-bit priority encoder using basic gates , and if i want to add one more bit how many gates i must add? and then to implement an SR flip-flop using D flip-flops — first with asynchronous Set, and then with asynchronous Reset.
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Formal Verification Engineer

Interviewed at NVIDIA

4.5
May 25, 2025

I was asked to implement a 4-bit priority encoder using basic gates , and if i want to add one more bit how many gates i must add? and then to implement an SR flip-flop using D flip-flops — first with asynchronous Set, and then with asynchronous Reset.

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