What are the phases of UVM? How to swap two variables given only the addresses of those variables? Pipeline Hazards?
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
Count number of bit 1s in an integer
How to verify a fifo?
I just had been asked to define myself, and if have any questions.
Your'e given a matrix MxN of 0's and 1's. everytime you encounter 1 cell, you need to put 0's in the rows and columns.
Design a state machine that will print '1' when a binary string divisible by 5 is input. E.g. '0101', '1111' all must output 1.
What's the different of rand and randc
Design a Counter verification environment.
asked about verification environment of system, Coverage questions
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
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