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Design Verification Engineer Interview Questions
3,718 design verification engineer interview questions shared by candidates
Name a job you'd never want
Draw internal cmos crcuit for nand, nor gates. Bandwidth of opamps. Solve basic opamp circuits. They focus more on fundamentals of both analog and logic design. Also focussed on vhdl as it was used a lot for modeling in that group.
Make an AND gate from a 2-to-1 mux and make a k-map for that set-up, write code (any language) to arrange a N-sized list of numbers in ascending or descending order, what is set time, hold time, and metastability, divide a clock signal by three
Questions related to Pipelining, Interrupt Handling.
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
What was you favourite experience in Grand Theft Auto V and in Red Dead Redemption 2?
Why is quality assurance important?
They mainly asked about my MTech Project since it was based Non-linear FEM.
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