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Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
How do you handle conflict in the workplace?
Various questions related to integrated analog/mixed signal IP. CSAs, BGRs and general guidelines of DSP were discussed.
OOPS Concepts , Frameworks, data structures, Python basics
Describe your CV and previous experience. Talk about my bachelor thesis.
verify a FIFO using formal verification techniques and methods to resolve complexity
Implement using simple digital components a system that only transmits a stable signal (only if the logical value is stored N times)
TECH: 1. write a code that generates a random phone number 2. You have 4 processes: A, B, C, D. If any of them finishes kill B. When all of them are finished print Done. (use fork join) 3. inheritance, asks you when a child had the same function as a parent what will it print when it is called. what is different when the function is virtual. can a child object be assignment to a parent and vice versa? after the assignment you call the function and they ask you what will be printed 4. make a sequence for burst write and read, for a 32 bit (I cant remember but there was a number here also?) K memory. (you need to write an item first and then show how it is used in the sequence)
Tell me why i should hire you. Share with me some of the projects you did in school
Verify a protocol and tell checkers
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