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Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Computer architecture, cache related question.
Sum up the elements in an array
32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
How would you handle disagreement with colleague
draw a circut with 3 mux
build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
Given a Adder and was told to verify it? What are the testcases that you consider?
Questions mainly on SV and UVM. Very few Questions on protocols. Few Puzzels. SV UVM question were in depth. this involved writing various codes for driver, sequence etc. Constraints related questions on array. Assertions were aslo asked
One hour phone interview. asked basic questions on OOPs concepts, system verilog, FSM, latches.
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