Lot about past experience and projects, Arbiter design, OOPS concepts, scripting, verilog, Asynchronous/synchronous FIFO, Computer Architecture, Verification concepts. However most of it was focussed on prior experience.
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Output the sum of the largest series of consecutive values, in an infinite arbitrary series of numbers.
Implementing MIPS using pipelining
Questions mainly on SV and UVM. Very few Questions on protocols. Few Puzzels. SV UVM question were in depth. this involved writing various codes for driver, sequence etc. Constraints related questions on array. Assertions were aslo asked
Was asked about basics of computer architecture, Digital Design and verilog
Create an application like Visio.
One hour phone interview. asked basic questions on OOPs concepts, system verilog, FSM, latches.
Q : Draw the FSM diagram for a given case considering mealey machine and taking the overlap cases.
Given a Adder and was told to verify it? What are the testcases that you consider?
build a function that get: s - sum of puckets n - number of puckets MIN - minimu value of a pucket MAX - maximum value of a pucket return an array in length n that each pucket have a value between MIN and MAX and the sum of all puckets is s. all puckets are random.
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