UVM, system verilog, C++, puzzles and ethernet related
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
SystemVerilog, UVM environment, AHB, AXI, Ethernet
What challenges have you faced and how did you overcome them?
Aptitude, C++, Verilog, Digital Design basics and logical reasoning
Using constrained randomization what types of functional coverage would you expect to see on a PCIe bus?
Imagine you and HR manager meet in the elevator. What would you say (within 1 min) to convince him/her to hire you?
A question on FIFO depth and Constrained Random Verification
Written test process Interview Very tough
What animal would you describe yourself as?
How would you verify a microwave clock/timer is working correctly?
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