You have a pen and a whiteboard, how would you test it?
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
Basics
About counters ,flipflops gates ?
What are is your weakness?
Standard coding test followed by a separate technical interview based around figuring out the root cause and solution to a real-life issue.
Basic digital Questions, SV, UVM,C
1) tell me about yourself? 2. started from digital electronics, questions from mux.design 10:1 mux from 3:1 mux.difference between synchronous and asynchronous design ,sequential and combinational circuits. 3.what is blocking and non blocking in verilog. 4.write a vcerilog code for d flipflop for asynchronous reset 5.write a verilog code for counter. 6.test bech for the above codes. 7.can we write always block inside initial and vise versa?(no procedural block can be implemented inside another procedural block) 8.how to implement always block function without using always block? 9.what is logic,reg,wire data types and their default value?signed and unsigned data types and their size. 10. simple aptitude problem on clock 8.
Why I want to join
Constraint writing Assertion writing on given waveform
As an ASIC verification Engineer Most of the questions were based on system Verilog and UVM. 1: Components of UVM, which components have you worked. 2: Phases in UVM 3: Assertions
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