How to deal with clock domain crossing issues, timings in logic circuits etc
Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
ou have 100 people standing in a line, each wearing either a black or white hat. Each person can see the hats of the people standing in front of them, but not their own hat or the hats of anyone behind them. Starting from the back of the line, each person is asked to announce the color of their own hat, and they can only say "black" or "white." How can you maximize the number of people who correctly guess the color of their hat?
What is polymorphism, how is it different from inheritance, give an example usage of polymorphism in Systemverilog testbench generation.
1. constraints 2. assertions 3. UVM topology
What are your previous experiences ?
Write a program to find the sum of numbers in a Fibonacci series upto n terms.
Technical test about mesurments setups, coding, electronic fundamentals
difference shallow copy and deep copy
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
About a time I stood up to authority. One of my top favorite interview questions of all time.
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