1.difference between dynamic,static ,short circuit power diddipation ,where and how it happens ,how to reduce them 2. power reduction technoques at logic and architectute level 3. verilog
Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
Design a digital circuit that on every third cycle calculates the average between the first and the second posedge and write it in verilog
do I know objective-oriented coding
- Switch 2 variable's content without temporary variable. - Create an array with all the numbers from 0 to Size - 1 in random order and without duplicates.
Draw out the circuit simple verilog code would synthesize to
To assemble mux 4x1 with mux 2x1
Verification plan of any given design, assertions, what is coverage?
Given read and write freq, how to calculate FIFO depth?
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
Do you have prior experience with UVM and System Verilog
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